1. Field of the Invention
The present invention relates to a method of forming at least an opening by utilizing a tri-layer structure, and more particularly, to a method of forming at least an opening by performing a multiple-step etching process.
2. Description of the Prior Art
As the semiconductor processes advance to very deep submicron era, such as 65 nm processes or beyond, controlling the critical dimension (CD) of components in the integrated circuits has become a critical issue in the art.
As the critical dimension (CD) keeps shrinking, the actual gate pattern and gate profile are influenced by aspect ratio of the gate in etching process. Furthermore, the AEI (after etch inspection) CD is susceptible to loading effect. There are different pattern densities in a chip (hence in a wafer). For etching, it is easy to happen loading effect between iso-region (region having isolated patterns) and dense-region (region having dense patterns).
Please refer to FIG. 1 and FIG. 2, which are schematic diagrams illustrating a conventional method of forming openings. As shown in FIG. 1, a substrate 10 is first provided. A film 12 is formed on the substrate 10, and a patterned mask 14 is formed on the film 12. The patterned mask 14 is utilized to define a predetermined pattern of the film 12, or even a predetermined pattern of the substrate 10. According to the predetermined pattern, an iso-region 22 (region having isolated patterns) and a dense-region 24 (region having dense patterns) are defined on the substrate 10.
As shown in FIG. 2, an etching process is subsequently performed on the film 12 by utilizing the patterned mask 14 as an etching mask to form openings 16 in the film 12 and to expose the substrate 10. Because the iso-region 22 possess larger openings 16 in surface area than dense-region 24, etchant can contact and react with more material in the iso-region 22, and more by-products are produced in the iso-region 22. Consequently, the influence on the surface of the wafer after the etching process is adversely different due to the loading effect. The loading effect undesirably makes the bottom AEI CD 25 of the resulted pattern larger than the predetermined CD 15 of the defined pattern in dense-region 24, and the difference between the bottom AEI CD 27 of the resulted pattern and the predetermined CD 17 of the defined pattern in the iso-region 22 is even more.
However, both an over-large CD bias of the patterns and an undesired profile of the patterns can lead to structural defeats in the chip or in the wafer. Therefore, there is still a need for a novel etching process to solve the issues of large CDs and bad loadings in iso-region/dense-region (I/D) as described above.